SPI protocol:
Serial peripheral interface: it is a 4-wire interface while in a three wire protocol the SDI and SDO pins are tied together
SDI pin (DIN pin) (MOSI pin) for input data.
SDO pin (Dout pin) (MISO pin) for output data.
SCLK pin (shift clock) (SCk) pin to sync data transfer between two chips.
CE pin (chip enable) (SS) it is used to initiate and terminate data transfer.
Working:
SPI has one shift registers , one on Master side and one in slave side and a clock generator on master side.
the names MOSI(Master Out Slave In) is given to the master's Serial data out pin. while MISO(Master In Slave Out) is given to the master's Serial data input pin.
These registers are 8bit long.
SCLK synchronizes transfer one bit at a time And during CE must stay HIGH.
To distinguish between read and Write operation,
Address byte is followed immediately by the data byte.
D7 bit of address byte is always 1 for write operation.
D7 bit of address byte is always 0 for a read operation.
CPOL(clock polarity) :
value =0 means base value of clock is zero.
value =1 means base value of clock is one.
CPHA(clock phase) :
value =0 means sample on leading clock
value =1 means sample on falling clock
Single-byte write mode :
You make CE=0
Begin by sending the 8 bit address,
Always remember the MSB goes out first, and since you are writing data, the first bit is Address 7 bit should always be equal to 1. After the 8 bit address goes the 8 bit data from the Master to slave through MOSI pin.
The data is shifted 1 bit at a time with the SCLK edge and at the end CE is set to 1 to indicate end of write cycle
Single-byte Read mode :
You make CE=0
Begin by sending the 8 bit address,
Always remember the MSB goes out first, and since you are reading data, the first bit is Address 7 bit should always be equal to 0. After the 8 bit address is sent through the MOSI, the 8 bit data on the same address is sent back by Slave on MISO pin.
The data is shifted 1 bit at a time with the SCLK edge and at the end CE is set to 1 to indicate end of write cycle
Multibyte burst write:
You make CE=0
Begin by sending the 8 bit address,
Always remember the MSB goes out first, and since you are writing data, the first bit is Address 7 bit should always be equal to 1. After the 8 bit address goes the 8 bit data from the Master to slave through MOSI pin.
The data is shifted 1 bit at a time with the SCLK edge and the only difference here is that after the 8 bit DAta byte no. 1 you can send next data byte without giving an new address. The SCLK after the first databyte will automatically increment the address to +1 of previous address.
at the end CE is set to 1 to indicate end of write cycle.
Multibyte burst Read:
You make CE=0
Begin by sending the 8 bit address,
Always remember the MSB goes out first, and since you are reading data, the first bit is Address 7 bit should always be equal to 0. After the 8 bit address is sent through the MOSI, the 8 bit data on the same address is sent back by Slave on MISO pin.
The data is shifted 1 bit at a time with the SCLK edge and the only difference here is that after the 8 bit Data byte no. 1 you can send next data byte without giving an new address. The SCLK after the first databyte will automatically increment the address to +1 of previous address.
at the end CE is set to 1 to indicate end of write cycle.
SPSR: SPI STATUS REGISTER gives the current status of ongoing SPI exchange
SPCR: SPI CONTROL REGISTER lets you select
1.) a device as MASTER or SLAVE using MSTR bit
2) Clock Phase and polarity using CPHA and CPOL
3) data order using DORD
4) Clock Frequency using SPR1 SPR0 and SPI2X from SPSR register
SPDR: SPI DATA REGISTER holds data for reading and writing.
The SS pin (SLAVE SELECT pin) has integral role to play in selecting the mode of operation of SPI
When in master mode, and SS as OUTPUT you can make it High or low.
When in master mode, and SS is INPUT, A high signal on SS pin will make it master and a low on SS pin will make it SLAVE
When in Slave mode, SS pin should always be INPUT
A simple Example: I have chosen AtMega16
Make sure you use change the PIN numbers according to the controller you are using.
*****************************************************
# include <avr/io.h>
int main(void)
{
DDRA = 0xff;
DDRB = (1<<6)|(1<<7)
SPCR= (1<<MSTR)|(1<<SPE)|(1<<SPR0)
while(1)
{
SPDR= 'H';
while(!(SPSR & (1<<SPIF)));
PORTA=SPDR;
}
return 0;
}
******************************************************
Try this code combining two SPI controllers and twitch it according to your need.
For the slave device make MSTR==0 and SS pin as input and have fun with SPI.
And feel free to ask questions around the circuit or code or its scope of use.
Serial peripheral interface: it is a 4-wire interface while in a three wire protocol the SDI and SDO pins are tied together
SDI pin (DIN pin) (MOSI pin) for input data.
SDO pin (Dout pin) (MISO pin) for output data.
SCLK pin (shift clock) (SCk) pin to sync data transfer between two chips.
CE pin (chip enable) (SS) it is used to initiate and terminate data transfer.
Working:
SPI has one shift registers , one on Master side and one in slave side and a clock generator on master side.
the names MOSI(Master Out Slave In) is given to the master's Serial data out pin. while MISO(Master In Slave Out) is given to the master's Serial data input pin.
These registers are 8bit long.
SCLK synchronizes transfer one bit at a time And during CE must stay HIGH.
To distinguish between read and Write operation,
Address byte is followed immediately by the data byte.
D7 bit of address byte is always 1 for write operation.
D7 bit of address byte is always 0 for a read operation.
CPOL(clock polarity) :
value =0 means base value of clock is zero.
value =1 means base value of clock is one.
CPHA(clock phase) :
value =0 means sample on leading clock
value =1 means sample on falling clock
Single-byte write mode :
You make CE=0
Begin by sending the 8 bit address,
Always remember the MSB goes out first, and since you are writing data, the first bit is Address 7 bit should always be equal to 1. After the 8 bit address goes the 8 bit data from the Master to slave through MOSI pin.
The data is shifted 1 bit at a time with the SCLK edge and at the end CE is set to 1 to indicate end of write cycle
Single-byte Read mode :
You make CE=0
Begin by sending the 8 bit address,
Always remember the MSB goes out first, and since you are reading data, the first bit is Address 7 bit should always be equal to 0. After the 8 bit address is sent through the MOSI, the 8 bit data on the same address is sent back by Slave on MISO pin.
The data is shifted 1 bit at a time with the SCLK edge and at the end CE is set to 1 to indicate end of write cycle
Multibyte burst write:
You make CE=0
Begin by sending the 8 bit address,
Always remember the MSB goes out first, and since you are writing data, the first bit is Address 7 bit should always be equal to 1. After the 8 bit address goes the 8 bit data from the Master to slave through MOSI pin.
The data is shifted 1 bit at a time with the SCLK edge and the only difference here is that after the 8 bit DAta byte no. 1 you can send next data byte without giving an new address. The SCLK after the first databyte will automatically increment the address to +1 of previous address.
at the end CE is set to 1 to indicate end of write cycle.
Multibyte burst Read:
You make CE=0
Begin by sending the 8 bit address,
Always remember the MSB goes out first, and since you are reading data, the first bit is Address 7 bit should always be equal to 0. After the 8 bit address is sent through the MOSI, the 8 bit data on the same address is sent back by Slave on MISO pin.
The data is shifted 1 bit at a time with the SCLK edge and the only difference here is that after the 8 bit Data byte no. 1 you can send next data byte without giving an new address. The SCLK after the first databyte will automatically increment the address to +1 of previous address.
at the end CE is set to 1 to indicate end of write cycle.
SPSR: SPI STATUS REGISTER gives the current status of ongoing SPI exchange
SPCR: SPI CONTROL REGISTER lets you select
1.) a device as MASTER or SLAVE using MSTR bit
2) Clock Phase and polarity using CPHA and CPOL
3) data order using DORD
4) Clock Frequency using SPR1 SPR0 and SPI2X from SPSR register
SPDR: SPI DATA REGISTER holds data for reading and writing.
The SS pin (SLAVE SELECT pin) has integral role to play in selecting the mode of operation of SPI
When in master mode, and SS as OUTPUT you can make it High or low.
When in master mode, and SS is INPUT, A high signal on SS pin will make it master and a low on SS pin will make it SLAVE
When in Slave mode, SS pin should always be INPUT
A simple Example: I have chosen AtMega16
Make sure you use change the PIN numbers according to the controller you are using.
*****************************************************
# include <avr/io.h>
int main(void)
{
DDRA = 0xff;
DDRB = (1<<6)|(1<<7)
SPCR= (1<<MSTR)|(1<<SPE)|(1<<SPR0)
while(1)
{
SPDR= 'H';
while(!(SPSR & (1<<SPIF)));
PORTA=SPDR;
}
return 0;
}
******************************************************
Try this code combining two SPI controllers and twitch it according to your need.
For the slave device make MSTR==0 and SS pin as input and have fun with SPI.
And feel free to ask questions around the circuit or code or its scope of use.
keep reading :)
Abheerup
